US 12,339,321 B2
Semiconductor device and method of failure analysis for semiconductor device
Shih-Wei Peng, Hsinchu (TW); Wei-Cheng Lin, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 5, 2022, as Appl. No. 17/857,556.
Claims priority of provisional application 63/267,390, filed on Feb. 1, 2022.
Prior Publication US 2023/0243888 A1, Aug. 3, 2023
Int. Cl. G01R 31/3185 (2006.01); G01R 31/307 (2006.01); G01R 31/317 (2006.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G06F 117/10 (2020.01); G06F 119/12 (2020.01)
CPC G01R 31/318525 (2013.01) [G01R 31/307 (2013.01); G01R 31/31717 (2013.01); G06F 30/396 (2020.01); G06F 30/398 (2020.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); G06F 2117/10 (2020.01); G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first scan flip-flop circuit (11) having an output terminal (111/Q);
a second scan flip-flop circuit (15) having an input terminal (151/SI);
a scan in path (SP) formed between the output terminal of the first scan flip-flop circuit and the input terminal of the second scan flip-flop circuit; and
a snorkel structure (20) connected to the scan in path,
wherein the snorkel structure is electrically connected to the output terminal (111/Q) of the first scan flip-flop circuit (11) and the input terminal of the second scan flip-flop circuit, and
wherein a second conductive structure (23) has a topmost conductive layer (233) buried in a dielectric layer (10) of the semiconductor device.