US 12,339,320 B2
Forward error correction (FEC) encoded physical layer test pattern
Fabio Bottoni, Milan (IT); and Alessandro Cavaciuti, San Donato Milanese (IT)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Apr. 21, 2023, as Appl. No. 18/304,568.
Claims priority of provisional application 63/439,932, filed on Jan. 19, 2023.
Prior Publication US 2024/0248135 A1, Jul. 25, 2024
Int. Cl. G01R 31/00 (2006.01); G01R 31/3183 (2006.01)
CPC G01R 31/318385 (2013.01) [G01R 31/318371 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a physical layer test pattern for testing operation of a device;
generating a forward error correction (FEC) framed test pattern by deriving from the physical layer test pattern a plurality of test pattern payloads, translating the plurality of test pattern payloads to a plurality of inverse encoded test pattern payloads that, when FEC encoded, produce the plurality of test pattern payloads, and forming the FEC framed test pattern with a sequence of codewords each of which includes a respective one of the plurality of inverse encoded test pattern payloads; and
applying the FEC framed test pattern to the device to test physical layer operation of the device and to obtain FEC error statistics and information indicating operational performance of the device as a result of stress caused by the physical layer test pattern.