US 12,339,202 B2
Method of failure analysis for defect locations
Qiang Chen, Shanghai (CN); and Jinde Gao, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed on Feb. 16, 2023, as Appl. No. 18/170,437.
Claims priority of application No. 202210185334.5 (CN), filed on Feb. 28, 2022.
Prior Publication US 2023/0273101 A1, Aug. 31, 2023
Int. Cl. G01N 1/36 (2006.01); G01N 23/04 (2018.01); H01J 37/31 (2006.01); H01J 37/317 (2006.01)
CPC G01N 1/36 (2013.01) [G01N 23/04 (2013.01); H01J 37/3178 (2013.01); G01N 2001/366 (2013.01); G01N 2223/6116 (2013.01); H01J 2237/31749 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A failure analysis method for locating a defect position, comprising following steps:
step 1, providing a chip sample having a metal layer, wherein the metal layer has an open circuit defect;
step 2, delaminating the chip sample to expose a top surface of the metal layer having the open circuit defect;
step 3, depositing a metal conductive layer on the metal layer of the chip sample;
step 4, removing a portion of the metal conductive layer from a top surface the metal layer to expose the metal layer;
step 5, depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer of the chip sample;
step 6, preparing a TEM (Transmission Electron Microscopy) slice sample from the chip sample, wherein the TEM slice sample comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer;
step 7, performing a VC (voltage contrast) analysis on the TEM slice sample to determine the defect position of the open circuit defect; and
step 8, analyzing the defect position of the open circuit defect on the TEM slice sample.