US 12,016,188 B2
Semiconductor memory device
Hyuncheol Kim, Seoul (KR); Yongseok Kim, Suwon-si (KR); Dongsoo Woo, Seoul (KR); and Kyunghwan Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 14, 2022, as Appl. No. 17/840,213.
Claims priority of application No. 10-2021-0078919 (KR), filed on Jun. 17, 2021.
Prior Publication US 2022/0406848 A1, Dec. 22, 2022
Int. Cl. G11C 13/00 (2006.01); H10K 10/50 (2023.01); H10K 19/00 (2023.01); H10K 85/20 (2023.01)
CPC H10K 19/202 (2023.02) [G11C 13/0014 (2013.01); G11C 13/0069 (2013.01); H10K 10/50 (2023.02); H10K 85/221 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including
a first source/drain area,
a channel area, and
a second source/drain area arranged in the first horizontal direction;
a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas of the plurality of semiconductor patterns;
a plurality of word lines on the upper surfaces or the side surfaces of the channel areas of the plurality of semiconductor patterns; and
a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including
a first electrode,
a second electrode, and
a resistive switch material layer between the first electrode and the second electrode and including carbon nanotubes.