CPC H10B 63/30 (2023.02) [H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A semiconductor memory device, comprising:
first conductive lines provided on a substrate and extending in a first direction in parallel, each of the first conductive lines including a first end portion and a second end portion that are opposite to each other, the first direction being parallel to a top surface of the substrate;
first selection transistors respectively connected to the first end portions of the first conductive lines; and
second selection transistors respectively connected to the second end portions of the first conductive lines, wherein:
each of the first selection transistors has a first gate width, and
each of the second selection transistors has a second gate width smaller than the first gate width.
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