CPC H10B 43/27 (2023.02) [G11C 16/10 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/7926 (2013.01)] | 14 Claims |
1. A memory device, comprising:
an alternating stack of insulating layers and control gate layers;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure comprising a memory film and a vertical semiconductor channel located within the memory opening,
wherein the memory film comprises a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer;
wherein the resonant tunneling barrier stack comprises at least two semiconductor quantum wells.
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