| CPC H10B 10/12 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 22/12 (2013.01); H01L 23/528 (2013.01); H04N 21/42692 (2013.01); H10B 10/00 (2023.02); H10B 41/35 (2023.02); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01); H01L 2924/1437 (2013.01)] | 18 Claims |
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1. A memory cell comprising:
a substrate having a front side and a back side, wherein a transistor of the memory cell is formed on the front side, and wherein the back side is opposite of the front side;
a first interconnect layer on the front side to provide a bit line of the memory cell;
a second interconnect layer on the front side to provide a word line of the memory cell;
a third interconnect layer on the back side to provide a supply voltage to the memory cell; and
a fourth interconnect layer on the back side to provide a ground voltage to the memory cell,
wherein the first interconnect layer corresponds to a first bit line portion of the bit line that abuts a second bit line portion of an adjacent memory cell; and
wherein the third interconnect layer is wider than each of the first interconnect layer and the second interconnect layer.
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