US 12,015,471 B2
Integrated circuit for controlling a communication scheme
Yutaka Murakami, Kanagawa (JP); Tomohiro Kimura, Osaka (JP); and Mikihiro Ouchi, Osaka (JP)
Assigned to SUN PATENT TRUST, New York, NY (US)
Filed by Sun Patent Trust, New York, NY (US)
Filed on Mar. 20, 2023, as Appl. No. 18/123,505.
Application 18/123,505 is a continuation of application No. 17/243,988, filed on Apr. 29, 2021, granted, now 11,658,733.
Application 17/243,988 is a continuation of application No. 16/790,358, filed on Feb. 13, 2020, granted, now 11,070,281, issued on Jul. 20, 2021.
Application 16/790,358 is a continuation of application No. 16/017,244, filed on Jun. 25, 2018, granted, now 10,623,084, issued on Apr. 14, 2020.
Application 16/017,244 is a continuation of application No. 15/617,550, filed on Jun. 8, 2017, granted, now 10,044,432, issued on Aug. 7, 2018.
Application 15/617,550 is a continuation of application No. 15/202,924, filed on Jul. 6, 2016, granted, now 9,806,793, issued on Oct. 31, 2017.
Application 15/202,924 is a continuation of application No. 14/582,610, filed on Dec. 24, 2014, granted, now 9,426,631, issued on Aug. 23, 2016.
Application 14/582,610 is a continuation of application No. 14/110,783, granted, now 8,989,237, issued on Mar. 24, 2015, previously published as PCT/JP2012/002676, filed on Apr. 18, 2012.
Claims priority of application No. 2011-093539 (JP), filed on Apr. 19, 2011; application No. 2011-102099 (JP), filed on Apr. 28, 2011; application No. 2011-118453 (JP), filed on May 26, 2011; application No. 2011-140747 (JP), filed on Jun. 24, 2011; and application No. 2011-192123 (JP), filed on Sep. 2, 2011.
Prior Publication US 2023/0231617 A1, Jul. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 40/22 (2009.01); H04B 7/0456 (2017.01); H04B 7/06 (2006.01); H04B 7/155 (2006.01); H04L 5/00 (2006.01); H04L 25/03 (2006.01); H04L 27/26 (2006.01); H04L 27/34 (2006.01); H04W 4/06 (2009.01); H04B 7/0413 (2017.01)
CPC H04B 7/15542 (2013.01) [H04B 7/0456 (2013.01); H04B 7/0604 (2013.01); H04L 5/0053 (2013.01); H04L 25/03171 (2013.01); H04L 25/0391 (2013.01); H04L 25/03949 (2013.01); H04L 27/2614 (2013.01); H04L 27/34 (2013.01); H04W 4/06 (2013.01); H04W 40/22 (2013.01); H04B 7/0413 (2013.01); H04L 5/0023 (2013.01)] 4 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
generation circuitry, which, in operation, controls generating one or more transmission signals; and
transmission circuitry, which, in operation, controls transmitting control information and the one or more transmission signals to a communication apparatus, the control information indicating a transmission scheme among a plurality of transmission schemes;
wherein
in a first scheme of the plurality of transmission schemes, the one or more transmission signals is generated by precoding first modulation signals and second modulation signals with precoding matrixes being changed among each symbol, and
in a second scheme of the plurality of transmission schemes, the one or more transmission signals is generated by precoding the first modulation signal and the second modulation signal with a precoding matrix being same among each symbol.