US 12,015,414 B2
Dual digital phase lock loop with unmodulation coupling
Menno Tjeerd Spijker, Richmond Hill (CA)
Assigned to RENESAS ELECTRONICS AMERICA INC., Milpitas, CA (US)
Filed by RENESAS ELECTRONICS AMERICA INC., Milpitas, CA (US)
Filed on Oct. 7, 2022, as Appl. No. 17/961,741.
Prior Publication US 2024/0120924 A1, Apr. 11, 2024
Int. Cl. H03L 7/07 (2006.01); H03L 7/107 (2006.01); H03L 7/23 (2006.01); H04L 7/033 (2006.01)
CPC H03L 7/07 (2013.01) [H03L 7/1075 (2013.01); H03L 7/23 (2013.01); H04L 7/0337 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an analog phase-lock loop (APLL) configured to output a first signal;
a first digital phase-lock loop (DPLL) configured to output a second signal; and
a second DPLL configured to output a third signal, wherein:
a combination of the first signal and the second signal is being used to generate a first output clock signal; and
a difference resulting from a subtraction of the second signal from the third signal is being used to generate a second output clock signal.