US 12,015,411 B2
Testable time-to-digital converter
Emil Gizdarski, Cupertino, CA (US); and Anubhav Sinha, Hyderabad (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on May 24, 2022, as Appl. No. 17/752,774.
Claims priority of application No. 202141023266 (IN), filed on May 25, 2021.
Prior Publication US 2022/0385280 A1, Dec. 1, 2022
Int. Cl. H03K 5/131 (2014.01); G04F 10/00 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/131 (2013.01) [G04F 10/005 (2013.01); H03K 2005/00058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delay selector, comprising:
a first multiplexer having a first input coupled to an input of the delay selector;
a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
a second multiplexer having a first input coupled to an output of the first multiplexer; and
a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer.