US 12,015,408 B2
Flip flop including serial stack structure transistors
Hyunchul Hwang, Suwon-si (KR); and Minsu Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 4, 2022, as Appl. No. 17/712,465.
Claims priority of application No. 10-2021-0049580 (KR), filed on Apr. 16, 2021.
Prior Publication US 2022/0337231 A1, Oct. 20, 2022
Int. Cl. H03K 3/012 (2006.01); H03K 3/013 (2006.01); H03K 3/356 (2006.01)
CPC H03K 3/356191 (2013.01) [H03K 3/012 (2013.01); H03K 3/013 (2013.01); H03K 3/356121 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A flip flop comprising:
a precharge circuit configured to charge a first node by bridging a power voltage node and the first node according to a voltage level of a clock signal, the pre-charge circuit including at least two PMOS transistors arranged directly in series, the at least two PMOS transistors configured to simultaneously receive a same clock signal;
a discharge circuit configured to discharge the first node by bridging the first node and a ground node according to an input signal and the clock signal;
a second node configured to be charged or discharged according to a voltage level of the first node; and
an additional discharge circuit between the discharge circuit and the ground node includes at least two NMOS transistors arranged in parallel, the at least two NMOS transistors configured to simultaneously receive the same clock signal.