US 12,015,404 B2
Logic process-based level conversion circuit of flash field programmable gate array (FPGA)
Zhengzhou Cao, Wuxi (CN); Yueer Shan, Wuxi (CN); Zhenkai Ji, Wuxi (CN); Jing Sun, Wuxi (CN); Chunyan He, Wuxi (CN); and Guangming Li, Wuxi (CN)
Assigned to WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed by WUXI ESIONTECH CO., LTD., Wuxi (CN)
Filed on Sep. 8, 2022, as Appl. No. 17/940,001.
Application 17/940,001 is a continuation of application No. PCT/CN2022/102650, filed on Jun. 30, 2022.
Claims priority of application No. 202111582292.0 (CN), filed on Dec. 22, 2021.
Prior Publication US 2023/0006672 A1, Jan. 5, 2023
Int. Cl. H03K 19/173 (2006.01)
CPC H03K 19/1733 (2013.01) 13 Claims
OG exemplary drawing
 
1. A logic process-based level conversion circuit of a flash field programmable gate array (FPGA) comprising a first-stage conversion module, an intermediate-stage conversion module, and a drive-stage conversion module, wherein the first-stage conversion module, the intermediate-stage conversion module, and the drive-stage conversion module are successively cascaded, wherein
the first-stage conversion module is configured to convert an input first signal of a VDD-GND voltage domain into a second signal of a VP1-GND voltage domain and output the second signal to the intermediate-stage conversion module; the intermediate-stage conversion module is configured to convert the input second signal of the VP1-GND voltage domain into a third signal of a VP1-VN voltage domain and output the third signal to the drive-stage conversion module; and the drive-stage conversion module is configured to convert the input third signal of the VP1-VN voltage domain into a drive signal of a VP2-VN voltage domain and output a word line for driving the flash FPGA; and
a logic process is controlled to output a corresponding voltage combination to complete an erasure operation or a programming operation on the flash FPGA, wherein the voltage combination comprises a core low voltage VDD, an intermediate voltage VP1, a drive-stage voltage VP2, and a negative voltage VN, wherein the core low voltage VDD, the intermediate voltage VP1, the drive-stage voltage VP2, and the negative voltage VN are provided by the logic process, wherein GND is a grounding voltage and VP2≥VP1≥VDD.