CPC H03K 19/018521 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); H03K 17/6872 (2013.01)] | 18 Claims |
1. A semiconductor apparatus comprising:
a global dock tree configured to drive a system dock signal to a complementary metal oxide semiconductor (CMOS) level to generate a first distribution dock signal and configured to drive the system dock signal to a current mode logic (CML) level to generate a second distribution dock signal;
a data output circuit configured to output data based on the first distribution dock signal; and
a data input circuit configured to receive the data based on the second distribution clock signal.
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