US 12,015,087 B2
Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
Bernhard Sell, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 29, 2022, as Appl. No. 17/956,763.
Application 14/569,166 is a division of application No. 13/995,634, granted, now 8,941,214, issued on Jan. 27, 2015, previously published as PCT/US2011/066991, filed on Dec. 22, 2011.
Application 17/956,763 is a continuation of application No. 17/475,196, filed on Sep. 14, 2021, granted, now 11,784,257.
Application 17/475,196 is a continuation of application No. 16/838,359, filed on Apr. 2, 2020, granted, now 11,164,975, issued on Nov. 2, 2021.
Application 16/838,359 is a continuation of application No. 16/393,290, filed on Apr. 24, 2019, granted, now 10,651,310, issued on May 12, 2020.
Application 16/393,290 is a continuation of application No. 15/275,072, filed on Sep. 23, 2016, granted, now 10,319,843, issued on Jun. 11, 2019.
Application 15/275,072 is a continuation of application No. 14/569,166, filed on Dec. 12, 2014, granted, now 9,711,410, issued on Jul. 18, 2017.
Prior Publication US 2023/0013575 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/7853 (2013.01) [H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/3083 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 27/1211 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/16 (2013.01); H01L 29/165 (2013.01); H01L 29/41791 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66772 (2013.01); H01L 29/66795 (2013.01); H01L 29/6681 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/7854 (2013.01); H01L 29/7856 (2013.01); H01L 29/786 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H01L 2924/13067 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor body above a substrate;
a gate electrode stack over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack, a first source or drain region in the semiconductor body at a first side of the gate electrode stack, and a second source or drain region in the semiconductor body at a second side of the gate electrode stack, the second side opposite the first side;
a first sidewall spacer adjacent to the first side of the gate electrode stack and over the first source or drain region, the first source or drain region having a width adjacent to the channel region and beneath the first sidewall spacer, the width greater than a width of the channel region of the semiconductor body, wherein the width of the first source or drain region is approximately 6-40% greater than the width of the channel region; and
a second sidewall spacer adjacent to the second side of the gate electrode stack and over the second source or drain region.