US 12,015,079 B2
Transistor with single termination trench having depth more than 10 microns
Noel Hoilien, Minneapolis, MN (US); Peter West, Minneapolis, MN (US); and Rajesh Appat, Eagan, MN (US)
Assigned to Polar Semiconductor, LLC, Bloomington, MN (US)
Filed by Polar Semiconductor, LLC, Bloomington, MN (US)
Filed on Aug. 30, 2021, as Appl. No. 17/460,747.
Prior Publication US 2023/0065066 A1, Mar. 2, 2023
Int. Cl. H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7393 (2013.01) [H01L 29/1095 (2013.01); H01L 29/66325 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of fabricating a transistor, comprising:
depositing a first epitaxial layer;
depositing a second epitaxial layer on the first epitaxial layer;
ion implanting the second epitaxial layer to form a base layer along a top surface of the second epitaxial layer and implanting a source into the base layer, wherein the base layer is a base of the transistor;
forming a single termination trench in the second epitaxial layer by etching the second epitaxial layer through the base layer so that the base layer is on either side of the trench, wherein a depth of the termination trench is greater than 10 microns;
driving the source implanting by heating the source;
filling the termination trench with a dielectric material,
wherein the base layer on either side of the trench is in direct contact with the dielectric material; and
depositing a contact glass on the dielectric material.