	US 12,015,078 B2
	Manufacturing method of semiconductor power device
Wei Liu, Suzhou (CN); Zhenyi Xu, Suzhou (CN); Zhendong Mao, Suzhou (CN); and Xin Wang, Suzhou (CN)
Assigned to SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD., Jiangsu (CN)
Appl. No. 17/622,021
Filed by SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD., Jiangsu (CN)
PCT Filed Nov. 12, 2020, PCT No. PCT/CN2020/128371 § 371(c)(1), (2) Date Dec. 22, 2021, PCT Pub. No. WO2022/082902, PCT Pub. Date Apr. 28, 2022.
Claims priority of application No. 202011127631.1 (CN), filed on Oct. 20, 2020.
Prior Publication US 2023/0268420 A1, Aug. 24, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01)

CPC H01L 29/66734 (2013.01) [H01L 21/3083 (2013.01); H01L 29/401 (2013.01); H01L 29/407 (2013.01); H01L 29/66719 (2013.01); H01L 29/7813 (2013.01)]

9 Claims

1. A manufacturing method of a semiconductor power device, comprising:

forming a first insulating layer on an n-type substrate and etching the first insulating layer to form an opening;

forming an insulating sidewall in the opening;

etching the n-type substrate using the first insulating layer and the insulating sidewall as a mask to form a first groove in the n-type substrate;

forming a second insulating layer and a shield gate in the first groove;

forming a third insulating layer on a surface of the shield gate;

etching off the insulating sidewall; and etching the n-type substrate using the first insulating layer, the second insulating layer, and the third insulating layer as a mask to form a second groove in the n-type substrate.