US 12,015,056 B2
Field effect transistor with controllable resistance
Yulong Li, Westchester, NY (US); Paul M. Solomon, Westchester, NY (US); and Siyuranga Koswatta, Carmel, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 25, 2023, as Appl. No. 18/306,359.
Application 18/306,359 is a division of application No. 17/474,260, filed on Sep. 14, 2021, granted, now 11,855,149.
Application 17/474,260 is a division of application No. 16/747,027, filed on Jan. 20, 2020, granted, now 11,177,349, issued on Nov. 16, 2021.
Application 16/747,027 is a division of application No. 16/434,711, filed on Jun. 7, 2019, granted, now 10,586,849, issued on Mar. 10, 2020.
Application 16/434,711 is a continuation of application No. 15/850,098, filed on Dec. 21, 2017, granted, now 10,374,041, issued on Aug. 6, 2019.
Prior Publication US 2023/0268396 A1, Aug. 24, 2023
Int. Cl. H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/68 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 29/80 (2006.01); H10B 12/00 (2023.01); H10B 41/30 (2023.01); H10B 51/30 (2023.01); H10B 63/00 (2023.01)
CPC H01L 29/1045 (2013.01) [H01L 29/0646 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/4983 (2013.01); H01L 29/516 (2013.01); H01L 29/66431 (2013.01); H01L 29/66659 (2013.01); H01L 29/66977 (2013.01); H01L 29/685 (2013.01); H01L 29/785 (2013.01); H01L 29/7881 (2013.01); H01L 29/802 (2013.01); H10B 12/30 (2023.02); H10B 41/30 (2023.02); H10B 51/30 (2023.02); H10B 63/00 (2023.02); H01L 29/66825 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/788 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region;
a conductive gate stack formed over the channel region, the conductive gate stack including;
a first gate dielectric layer on the channel region;
a second gate dielectric layer on the first gate dielectric layer;
a charge storage layer between the first gate dielectric layer and the second gate dielectric layer,
wherein the semiconductor device is configured to store a connection weight corresponding to a crosspoint device.
 
9. A semiconductor device comprising:
a source terminal;
a drain terminal, wherein the source terminal and the drain terminal are formed on either sides of a channel region designated on a substrate;
an energy barrier adjacent to the source terminal and the channel region; and
a conductive gate stack formed over the channel region, the conductive gate stack including:
at least one gate dielectric layer on the channel region; and
a gate electrode on the at least one gate dielectric layer;
a capacitor connected directly to the gate electrode and configured to store a charge indicative of a connection weight corresponding to a crosspoint device.