US 12,015,042 B2
Structure and material engineering methods for optoelectronic devices signal to noise ratio enhancement
Papo Chen, San Jose, CA (US); Schubert Chu, San Francisco, CA (US); Errol Antonio C Sanchez, Tracy, CA (US); John Timothy Boland, Aptos, CA (US); Zhiyuan Ye, San Jose, CA (US); Lori Washington, Union City, CA (US); Xianzhi Tao, San Jose, CA (US); Yi-Chiau Huang, Fremont, CA (US); and Chen-Ying Wu, Santa Clara, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Feb. 21, 2020, as Appl. No. 16/797,807.
Prior Publication US 2021/0265416 A1, Aug. 26, 2021
Int. Cl. H01L 27/146 (2006.01); H01L 31/18 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 31/1892 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
forming an interconnect structure over a front side of a sensor substrate;
thinning the sensor substrate from a back side of the sensor substrate;
etching trenches into the sensor substrate;
pre-cleaning an exposed surface of the sensor substrate;
epitaxially growing a charge layer directly on the back side of the pre-cleaned exposed surface of the sensor substrate and within the trenches; and
forming isolation structures within the etched trenches.