US 12,015,015 B2
Semiconductor package and semiconductor module including the same
Byung Jun Bang, Icheon-si (KR); and Ju Il Eom, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 10, 2023, as Appl. No. 18/108,503.
Application 18/108,503 is a continuation of application No. 17/398,646, filed on Aug. 10, 2021, granted, now 11,605,615.
Claims priority of application No. 10-2021-0050588 (KR), filed on Apr. 19, 2021.
Prior Publication US 2023/0197687 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 25/105 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06586 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a substrate including a first bonding pad and a first conductive pattern, wherein the first bonding pad is in contact with the first conductive pattern;
a lower semiconductor chip stacked over the substrate, wherein the lower semiconductor chip includes a first lower chip pad;
an upper semiconductor chip stacked over the lower semiconductor chip, wherein the upper semiconductor chip includes a first upper chip pad;
a first lower bonding wire connecting the first bonding pad to the first lower chip pad; and
a first upper bonding wire connecting the first bonding pad to the first upper chip pad,
wherein the first bonding pad is positioned between the first conductive pattern and the first semiconductor chip,
wherein the first lower bonding wire is connected to a first portion of the first bonding pad and the first upper bonding wire is connected to a second portion of the first bonding pad, and
wherein the first portion of the first bonding pad is farther from the first conductive pattern than the second portion of the first bonding pad.
 
9. A semiconductor package comprising:
a substrate including a first bonding pad exposed on a top surface of the substrate and a first conductive via formed within the substrate, wherein the first bonding pad and the first conductive via are electrically connected to each other;
a first semiconductor chip stacked over the substrate;
a second semiconductor chip stacked over the first semiconductor chip,
wherein the first semiconductor chip includes a first chip pad exposed on a top surface of the first semiconductor chip, and
wherein the second semiconductor chip includes a second chip pad exposed on a top surface of the second semiconductor chip;
a first bonding wire connecting the first bonding pad to the first chip pad; and
a second bonding wire connecting the first bonding pad to the second chip pad,
wherein the first bonding wire is bonded to a first portion of the first bonding pad,
wherein the second bonding wire is bonded to a second portion of the first bonding pad, and
wherein a first distance between the first conductive via and the first portion of the first bonding pad is longer than a second distance between the first conductive via and the second portion of the first bonding pad.
 
13. A semiconductor module comprising:
a module substrate;
a semiconductor package stacked over the module substrate;
a package substrate including a first bonding pad exposed on a top surface of the package substrate and a first conductive via formed within the package substrate;
a semiconductor chip stack stacked over the package substrate, wherein the semiconductor chip stack includes a first chip pad and a second chip pad,
a first bonding wire electrically connecting the first bonding pad to the first chip pad; and
a second bonding wire electrically connecting the first bonding pad to the second chip pad,
wherein the first bonding wire is bonded to a first portion of the first bonding pad,
wherein the second bonding wire is bonded to a second portion of the first bonding pad,
wherein a first length of the first bonding wire is shorter than a second length of the second bonding wire, and
wherein a first distance between the first conductive via and the first portion of the first bonding pad is longer than a second distance between the first conductive via and the second portion of the first bonding pad.