US 12,015,013 B2
Die stack structure, semiconductor structure and method of fabricating the same
Ming-Fa Chen, Taichung (TW); Chao-Wen Shih, Hsinchu County (TW); Min-Chien Hsiao, Taichung (TW); Nien-Fang Wu, Chiayi (TW); Sung-Feng Yeh, Taipei (TW); and Tzuan-Horng Liu, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 21, 2022, as Appl. No. 17/676,239.
Application 17/676,239 is a continuation of application No. 16/886,698, filed on May 28, 2020, granted, now 11,264,362.
Prior Publication US 2022/0181301 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/304 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/3043 (2013.01); H01L 21/78 (2013.01); H01L 23/3157 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 24/94 (2013.01); H01L 2224/80001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A die stack structure, comprising:
a bottom tier semiconductor die comprising a semiconductor substrate and an interconnect structure, the semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the interconnect structure being disposed on a top surface of the second portion, a lateral dimension of the first portion being greater than a lateral dimension of the top surface of the second portion;
a top tier semiconductor die bonded to the bottom tier semiconductor die;
an insulating encapsulation disposed on the first portion and laterally encapsulating the second portion and the top tier semiconductor die; and
a redistribution circuit structure electrically connected with the bottom tier semiconductor die and the top tier semiconductor die, wherein the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.