US 12,015,003 B2
High density interconnection and wiring layers, package structures, and integration methods
John Knickerbocker, Monroe, NY (US); Mukta Ghate Farooq, Hopewell Junction, NY (US); and Katsuyuki Sakuma, Fishkill, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 29, 2021, as Appl. No. 17/488,968.
Prior Publication US 2023/0100769 A1, Mar. 30, 2023
Int. Cl. H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01P 3/00 (2006.01); H01P 11/00 (2006.01)
CPC H01L 24/20 (2013.01) [H01L 21/4857 (2013.01); H01L 21/4871 (2013.01); H01L 21/6835 (2013.01); H01L 23/3675 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/66 (2013.01); H01L 24/19 (2013.01); H01P 3/003 (2013.01); H01P 11/003 (2013.01); H01L 2221/68368 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6627 (2013.01); H01L 2224/2105 (2013.01); H01L 2924/17151 (2013.01); H01L 2924/19033 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An interconnect for a semiconductor device, the interconnect comprising:
a laminate substrate;
a first plurality of electrical devices in or on a surface of the laminate substrate;
a redistribution layer having a surface disposed on the surface of the laminate substrate using a handle layer;
a second plurality of electrical devices in or on the surface of the redistribution layer; and
a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices;
wherein the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other such that the first plurality of electrical devices and the second plurality of electrical devices are interconnected upon removal of the handle layer to form a dielectric structure and a conductor structure.