US 12,014,996 B2
Moisture hermetic guard ring for semiconductor on insulator devices
Mohammad Kabir, Portland, OR (US); Conor P. Puls, Portland, OR (US); Babita Dhayal, Aloha, OR (US); Han Li, Hillsboro, OR (US); Keith E. Zawadzki, Portland, OR (US); Hannes Greve, Portland, OR (US); Avyaya Jayanthinarasimham, Hillsboro, OR (US); Mukund Bapna, Hillsboro, OR (US); and Doug B. Ingerly, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/914,045.
Prior Publication US 2021/0407932 A1, Dec. 30, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 21/762 (2006.01); H01L 23/58 (2006.01); H01L 27/12 (2006.01)
CPC H01L 23/564 (2013.01) [H01L 21/76251 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 27/1203 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A device comprising:
a device layer adjacent to an interconnect layer, the device layer comprising a plurality of semiconductor devices and the interconnect layer comprising a plurality of metal interconnects;
a bonding layer on a support substrate and adjacent one of the interconnect layer or the device layer; and
a guard ring structure, wherein the guard ring structure laterally surrounds the semiconductor devices and the metal interconnects, extends through the bonding layer, the interconnect layer, and the device layer, and is in contact with the support substrate.