US 12,014,992 B2
Semiconductor package
Sen-Kuei Hsu, Kaohsiung (TW); Hsin-Yu Pan, Taipei (TW); and Chien-Chang Lin, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 9, 2022, as Appl. No. 17/984,195.
Application 17/984,195 is a continuation of application No. 16/914,480, filed on Jun. 29, 2020, granted, now 11,508,666.
Prior Publication US 2023/0061943 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/00 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01P 3/08 (2006.01); H03H 7/01 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 23/5383 (2013.01); H01L 23/66 (2013.01); H01P 3/081 (2013.01); H03H 7/0115 (2013.01); H01L 2223/6627 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an encapsulated structure, comprising a semiconductor die and an encapsulant laterally encapsulating the semiconductor die;
electrical connectors as inputs/outputs of the semiconductor package, deployed at a front side of the encapsulated structure;
a circuit layer, lying between the encapsulated structure and the electrical connectors; and
a passive filter, embedded in the circuit layer, and comprising:
a ground plane, electrically coupled to a reference voltage;
a power plane, overlapping the ground plane, wherein a power signal is delivered to the semiconductor die through the power plane; and
conductive patches, arranged as an array between the ground plane and the power plane, and are electrically connected to the ground plane.