US 12,014,980 B2
Semiconductor device
Suhyun Bark, Suwon-si (KR); Kyeongbeom Park, Hwaseong-si (KR); Jongmin Baek, Seoul (KR); Jangho Lee, Hwaseong-si (KR); Wookyung You, Hwaseong-si (KR); and Deokyoung Jung, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 9, 2023, as Appl. No. 18/446,524.
Application 18/446,524 is a continuation of application No. 17/866,782, filed on Jul. 18, 2022, granted, now 11,764,149.
Application 17/866,782 is a continuation of application No. 17/130,293, filed on Dec. 22, 2020, granted, now 11,424,182, issued on Aug. 23, 2022.
Claims priority of application No. 10-2020-0054420 (KR), filed on May 7, 2020.
Prior Publication US 2024/0030127 A1, Jan. 25, 2024
Int. Cl. H01L 21/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 23/528 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device comprising:
forming a transistor on a substrate;
forming a first interlayer insulating layer on the transistor;
forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
forming a surface treatment region in the etch stop layer by applying photon energy to a surface of the etch stop layer;
selectively forming an etch stop pattern on the surface treatment region of the etch stop layer;
forming a second interlayer insulating layer on the etch stop pattern and the etch stop layer;
forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
forming a via hole penetrating the etch stop pattern and the etch stop layer and exposing a top surface of the lower interconnection line; and
forming an upper interconnection line in the interconnection line hole and the via hole.