US 12,014,977 B2
Interconnection structure, method of fabricating the same, and semiconductor package including interconnection structure
Ji-Seok Hong, Yongin-si (KR); Dongwoo Kim, Cheonan-si (KR); Hyunah Kim, Cheonan-si (KR); Un-Byoung Kang, Hwaseong-Si (KR); and Chungsun Lee, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 19, 2023, as Appl. No. 18/199,824.
Application 18/199,824 is a division of application No. 17/324,569, filed on May 19, 2021, granted, now 11,688,679.
Claims priority of application No. 10-2020-0109118 (KR), filed on Aug. 28, 2020.
Prior Publication US 2023/0290718 A1, Sep. 14, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4857 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an interconnection structure, the method comprising:
forming a sacrificial pattern on a carrier substrate;
forming on the carrier substrate a first dielectric layer that has an opening, the sacrificial pattern being in the opening;
forming on the carrier substrate a first seed layer that conformally covers the sacrificial pattern, a top surface of the first dielectric layer, and an inner lateral surface and a bottom surface of the opening;
forming on the first seed layer a conductive layer that covers the first dielectric layer and fills the opening;
performing on the conductive layer a planarization process to form a pad that remains in the opening and to selectively remove the first seed layer from the top surface of the first dielectric layer;
forming a second dielectric layer on the first dielectric layer; and
forming a wiring pattern that penetrates the second dielectric layer and is coupled to the pad.