US 12,014,976 B2
Chip package structure including a silicon substrate interposer and methods for forming the same
Kuo Lung Pan, Zhunan Township (TW); Yu-Chia Lai, Zhunan Township (TW); Teng-Yuan Lo, Hsinchu (TW); Mao-Yen Chang, Kaohsiung (TW); Po-Yuan Teng, Hsinchu (TW); Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); Hao-Yi Tsai, Hsinchu (TW); and Tin-Hao Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Mar. 28, 2023, as Appl. No. 18/191,147.
Application 18/191,147 is a division of application No. 17/205,621, filed on Mar. 18, 2021, granted, now 11,646,255.
Prior Publication US 2023/0253300 A1, Aug. 10, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 23/3121 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/562 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a chip package structure, the method comprising:
forming a combination of an interposer core assembly and a package-side redistribution structure over a carrier substrate, wherein the interposer core assembly comprises at least one silicon substrate interposer and a molding compound interposer frame that surrounds the at least one silicon substrate interposer, wherein one of the at least one silicon substrate interposer comprises metal bonding structures which are topmost components of vertical signal paths that vertically extend through said one of the at least one silicon substrate interposer;
forming a die-side redistribution structure comprising die-side redistribution wiring interconnects over the interposer core assembly, where the die-side redistribution wiring interconnects comprise via structures that are formed directly on surfaces of the metal bonding structures; and
attaching at least two semiconductor dies to the die-side redistribution structure, wherein a first subset of die-side redistribution wiring interconnects within the die-side redistribution structure provides chip-to-chip signal paths between the at least two semiconductor dies.