US 12,014,972 B2
Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices
Ju-Il Choi, Seongnam-si (KR); Kwang-Jin Moon, Hwaseong-si (KR); Byung-Lyul Park, Seoul (KR); Jin-Ho An, Seoul (KR); and Atsushi Fujisaki, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 16, 2021, as Appl. No. 17/403,154.
Application 17/403,154 is a continuation of application No. 15/936,019, filed on Mar. 26, 2018, granted, now 11,094,612.
Application 15/936,019 is a continuation of application No. 14/858,572, filed on Sep. 18, 2015, abandoned.
Claims priority of application No. 10-2014-0126143 (KR), filed on Sep. 22, 2014.
Prior Publication US 2021/0375725 A1, Dec. 2, 2021
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/14 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/5329 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/03618 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05546 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05559 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/10 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16111 (2013.01); H01L 2224/16112 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16147 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary via electrode through a portion of a substrate, the preliminary via electrode including a conductive layer and a barrier layer surrounding a sidewall of the conductive layer;
partially removing the substrate to expose a portion of the preliminary via electrode;
forming a protection layer structure on the substrate to cover the exposed portion of the preliminary via electrode;
partially etching the protection layer structure and the barrier layer to form a protection layer pattern structure and a barrier layer pattern, respectively, wherein a portion of the conductive layer is exposed;
wet etching the exposed portion of the conductive layer to form a conductive pattern, wherein the barrier layer pattern is wet etched so that a portion of the barrier layer pattern above the conductive pattern has a gradually decreasing width from a bottom toward a top thereof, and the conductive pattern and the barrier layer pattern form a via electrode; and
forming a pad structure on the via electrode.