US 12,014,964 B2
Semiconductor package having an electrically insulating core with exposed glass fibres
Eung San Cho, Torrance, CA (US); Tomasz Naeve, Finkenstein (AT); and Petteri Palm, Regensburg (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE); and Infineon Technologies Americas Corp., El Segundo (CA)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Nov. 14, 2022, as Appl. No. 17/986,306.
Application 17/986,306 is a continuation of application No. 17/082,643, filed on Oct. 28, 2020, granted, now 11,502,012.
Application 17/082,643 is a continuation in part of application No. 16/774,357, filed on Jan. 28, 2020, granted, now 11,532,541.
Prior Publication US 2023/0077139 A1, Mar. 9, 2023
Int. Cl. H01L 23/14 (2006.01); H01L 23/482 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/142 (2013.01) [H01L 23/4827 (2013.01); H01L 23/49827 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an electrically insulating core having a first side, a second side opposite the first side and configured for mounting to a substrate, and an electrically conductive first via extending through a periphery region of the core, the periphery region defining an opening in the core, the core comprising glass fibres interwoven with epoxy material, the core having one or more regions at the second side where the glass fibres are exposed from the epoxy material;
a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than the core and comprising a first load terminal bond pad at a first side which faces a same direction as the first side of the core, a second load terminal bond pad at a second side which faces a same direction as the second side of the core, and a control terminal bond pad at the first side or the second side of the power semiconductor die;
a resin in the opening in the core and that encases the power semiconductor die;
a first contact pad plated on the first via at the second side of the core; and
a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.