	US 12,014,951 B2
	Semi-damascene structure with dielectric hardmask layer
Hoonseok Seo, Niskayuna, NY (US); Euibok Lee, Seoul (KR); and Taeyong Bae, Albany, NY (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 30, 2021, as Appl. No. 17/390,035.
Claims priority of provisional application 63/191,037, filed on May 20, 2021.
Prior Publication US 2022/0375785 A1, Nov. 24, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)

CPC H01L 21/76816 (2013.01) [H01L 21/32139 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01)]

11 Claims

1. A method of manufacturing a semi-damascene structure of a semiconductor device, the method comprising:

forming a 1^stintermetal dielectric layer;

forming a 1^sthardmask layer and at least one 1^stphotoresist pattern on the 1^stintermetal dielectric layer;

patterning at least one via hole penetrating through the 1^sthardmask layer and the 1^stintermetal dielectric using the at least one 1^stphotoresist pattern;

removing the at least one 1^stphotoresist pattern;

forming a metal structure in the at least one via hole such that the metal structure fills in the at least one via hole and extends on the 1^sthardmask layer;

patterning the metal structure to form at least one 1^sttrench penetrating at least the metal structure at a portion where the metal structure extends on the 1^sthardmask layer; and

filling the at least one 1^sttrench with a 2^ndintermetal dielectric layer.