US 12,014,793 B2
Method of screening non-volatile memory cells
Viktor Markov, Santa Clara, CA (US); and Alexander Kotov, San Jose, CA (US)
Assigned to Silicon Storage Technology, Inc., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Jul. 6, 2022, as Appl. No. 17/858,185.
Claims priority of provisional application 63/330,650, filed on Apr. 13, 2022.
Prior Publication US 2023/0335212 A1, Oct. 19, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/50016 (2013.01) [G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01); G11C 29/50004 (2013.01); G11C 2029/5004 (2013.01); G11C 2029/5006 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for screening memory cells, comprising:
erasing the memory cells;
weakly programming the memory cells to a modified erased state;
performing a first read operation on the memory cells after the erasing and the weakly programming;
screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1;
baking the memory cells after the first read operation;
performing a second read operation on the memory cells after the baking; and
screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.