| CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01)] | 20 Claims |
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1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage;
each one of the strings having at least one drain-side select gate transistor on a drain-side of the one of the strings connected to one of a plurality of bit lines and coupled to the memory cells of the one of the strings; and
a control means coupled to the plurality of word lines and the plurality of bit lines and the at least one drain-side select gate transistors and configured to:
determine a respective unique select gate voltage for each of a plurality of groupings of the memory cells, the unique select gate voltage being individually adapted for each of the plurality of groupings of the memory cells such that a different unique select gate voltage is determined for each of the plurality of groupings, and
apply the respective unique select gate voltages to the at least one drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the at least one drain-side select gate transistor of the selected ones of the strings during a memory operation,
wherein determining the respective unique select gate voltages includes, for each of the plurality of groupings of memory cells, (i) setting a select gate voltage as a detection threshold voltage, (ii) selectively adjusting the detection threshold voltage and setting the select gate voltage as the adjusted detection threshold voltage, and (iii) setting the respective unique select gate voltage in response to the adjusting of the detection threshold voltage.
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