US 12,014,782 B2
Memory device for adjusting magnitude of signal used to precharge bit line according to position of plug hole and operating method thereof
Jung Hyeong Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Dec. 23, 2021, as Appl. No. 17/561,228.
Claims priority of application No. 10-2021-0071813 (KR), filed on Jun. 2, 2021.
Prior Publication US 2022/0392544 A1, Dec. 8, 2022
Int. Cl. G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device including a memory block to which a plurality of lines are connected, the memory device comprising:
a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit;
a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines; and
a peripheral circuit configured to perform a read operation on memory cells of a first plug hole among the plurality of plug holes,
wherein the first plug hole includes at least two memory cells among the plurality of memory cells, and is connected to at least two bit lines among the plurality of bit lines,
wherein the peripheral circuit includes a voltage generator which is, during the read operation, configured to adjust a magnitude of a signal applied to at least two page buffers corresponding to the at least two bit lines among the plurality of page buffers to precharge the at least two bit lines according to a position of the first plug hole.