US 12,014,781 B2
Memory device supporting interleaved operations and memory system including the same
Won Jae Choi, Icheon-si (KR); and Jea Won Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 21, 2021, as Appl. No. 17/507,326.
Application 17/507,326 is a continuation in part of application No. 17/244,060, filed on Apr. 29, 2021, granted, now 11,733,921.
Claims priority of application No. 10-2020-0139606 (KR), filed on Oct. 26, 2020.
Prior Publication US 2022/0130464 A1, Apr. 28, 2022
Int. Cl. G11C 16/14 (2006.01); G11C 7/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 7/1039 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a first memory die including multiple planes each including a plurality of memory cells; and
a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die,
wherein the controller is configured to, after transferring an erase command to a plane among the multiple planes, transfer a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane, and
wherein the controller is configured to estimate an operation margin of the erase operation performed in the plane and adjust or change a sequence of the read command, the program command, and the check command to be transferred to the another plane.