US 12,014,775 B2
Write error counter for media management in a memory device
John Christopher M. Sancon, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 28, 2022, as Appl. No. 17/732,353.
Prior Publication US 2023/0352086 A1, Nov. 2, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0035 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01)] 31 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a counter;
a memory array having a plurality of memory cells; and
at least one controller configured to:
determine whether a memory cell snaps due to applying at least one pulse to the memory cell;
in response to determining that the memory cell does not snap, increment a count using the counter;
determine whether the count has reached a threshold; and
in response to determining that the count has reached the threshold, perform an action associated with the memory array.