US 12,014,764 B2
Memory device including row hammer preventing circuitry and an operating method of the memory device
Jungmin You, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 7, 2022, as Appl. No. 17/939,327.
Claims priority of application No. 10-2021-0121181 (KR), filed on Sep. 10, 2021.
Prior Publication US 2023/0079457 A1, Mar. 16, 2023
Int. Cl. G11C 11/406 (2006.01); G11C 11/4078 (2006.01)
CPC G11C 11/40618 (2013.01) [G11C 11/40615 (2013.01); G11C 11/4078 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A row hammer preventing circuitry, comprising:
a first table configured to store a count value representing a hit count and an address bit of each of a plurality of entries, each of the entries corresponding to access-requested target rows;
a second table including safe bits representing whether each of the plurality of entries is accessed twice or more and a safe bit counter representing the number of the safe bits having a logic low; and
a row hammer preventing logic configured to identify masking entries, on which a masking comparison is to be performed, among the plurality of entries stored in the first table on the basis of a value of the safe bit counter, to determine a hit or a miss on the basis of whether other bits except a most significant bit among address bits of an access-requested target row match other bits except a most significant bit among address bits of the masking entries, and to generate a first control signal indicating an additional refresh is to be performed on rows adjacent to rows corresponding to a masking entry whose hit count is greater than a first threshold value.