CPC G11C 11/1675 (2013.01) [G11C 11/161 (2013.01); G11C 11/1673 (2013.01); H10B 61/20 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02); H10N 52/80 (2023.02); H10N 52/85 (2023.02); G11C 11/1655 (2013.01)] | 10 Claims |
1. A semiconductor memory device, comprising:
data storage patterns having respective first sides and respective second sides;
a spin-orbit coupling (SOC) channel layer in common contact with the first sides of the data storage patterns, wherein the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns;
read access transistors connected between the second sides of respective ones of the data storage patterns and respective data lines;
a write access transistor connected between a first end of the SOC channel layer and a source line; and
a bit line connected to a second end of the SOC channel layer,
wherein each of the data storage patterns comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer in contact with the free layer.
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