US 12,014,698 B2
Dot-matrix display device and timer apparatus
Takanobu Suzuki, Itami (JP)
Assigned to Kyocera Corporation, Kyoto (JP)
Appl. No. 17/919,696
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Apr. 6, 2021, PCT No. PCT/JP2021/014629
§ 371(c)(1), (2) Date Oct. 18, 2022,
PCT Pub. No. WO2021/215239, PCT Pub. Date Oct. 28, 2021.
Claims priority of application No. 2020-077808 (JP), filed on Apr. 24, 2020.
Prior Publication US 2023/0162698 A1, May 25, 2023
Int. Cl. G09G 3/36 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 2310/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A dot-matrix display device comprising:
a display including
a plurality of gate signal lines extending in a first direction,
a plurality of source signal lines extending in a second direction intersecting with the first direction, and
a plurality of pixel circuits arranged at intersections of the plurality of gate signal lines and the plurality of source signal lines;
a converter circuit configured to
obtain a serial signal in synchronization with a first clock signal input from outside, the serial signal being input from outside through a serial interface, including address data for specifying a pixel circuit of the plurality of pixel circuits to undergo a refresh of image data, and including the image data to be provided to the specified pixel circuit and
convert the obtained serial signal to a parallel signal; and
a control circuit configured to generate, based on a second clock signal having a lower frequency than the first clock signal, a control signal for controlling timing of serial-to-parallel conversion performed by the converter circuit,
wherein each of the plurality of pixel circuits includes a latch circuit configured to retain the image data,
wherein a pixel circuit of the plurality of pixel circuits in which the image data is not refreshed, displays a still image using the image data retained in the latch circuit,
wherein the serial signal includes dummy data unusable for refresh, and the dummy data is transferred to the converter circuit subsequent to the address data and the image data, and
wherein a transfer period of the dummy data is an active period of a gate signal during which the gate signal based on the address signal is provided to each of the plurality of gate signal lines and an active period of a source signal during which the source signal based on the image data is provided to each of the plurality of source signal lines, and further the transfer period of the dummy data is shorter than a shorter one of a transfer period of the address data and a transfer period of the image data.