US 12,014,205 B2
Advanced register merging
Navneet Kakkar, Bangalore (IN); Sridhar Keladi, Bangalore (IN); and Diptanshu Ghosh, Bangalore (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 30, 2021, as Appl. No. 17/217,110.
Claims priority of application No. 202041014214 (IN), filed on Mar. 31, 2020.
Prior Publication US 2021/0303336 A1, Sep. 30, 2021
Int. Cl. G06F 30/327 (2020.01); G06F 9/46 (2006.01); G06F 30/3308 (2020.01); G06F 30/3323 (2020.01)
CPC G06F 9/466 (2013.01) [G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/3323 (2020.01)] 30 Claims
OG exemplary drawing
 
1. A logic-synthesis method, comprising:
loading a register-transfer level (RTL) description;
performing a first register-merging operation, configured to merge, into a first survivor register, a first plurality of registers of the RTL description;
outputting a first result of the first register-merging operation as a first output, comprising the first survivor register;
performing, via at least one computer processor, a second register-merging operation configured to merge, into a first equivalence class, a second plurality of registers that share a first functional equivalency based on the first output;
verifying, via the at least one computer processor, equivalence of the second plurality of registers within the first equivalence class; and
outputting at least the first equivalence class, in response to the verifying, as a second output comprising a second survivor register.