US 12,014,181 B2
Instruction execution method and instruction execution device
Weilin Wang, Beijing (CN); Yingbing Guan, Shanghai (CN); Lei Yi, Xi'an (CN); and Long Cheng, Shanghai (CN)
Assigned to SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD., Shanghai (CN)
Filed by Shanghai Zhaoxin Semiconductor Co., Ltd., Shanghai (CN)
Filed on Nov. 4, 2022, as Appl. No. 18/052,909.
Claims priority of application No. 202111385162.8 (CN), filed on Nov. 22, 2021.
Prior Publication US 2023/0161594 A1, May 25, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30087 (2013.01); G06F 9/30101 (2013.01); G06F 9/3818 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An instruction configuration and execution method, applicable to a microprocessor; wherein the microprocessor comprises a model specific register (MSR), and the instruction configuration and execution method comprises:
receiving a target instruction using an instruction cache; and
decoding the target instruction using an instruction translator to determine whether the target instruction has permission to read or write the model specific register in an unprivileged state, and whether a model specific register index of a specific instruction corresponds to a specific model specific register, so as to instruct the microprocessor to execute an instruction serialization operation;
wherein when the microprocessor determines that a previous instruction is completed, the microprocessor submits the target instruction and sends continuing operation information to the instruction cache, and the instruction cache receives a new target instruction.