US 12,014,178 B2
Folded instruction fetch pipeline
John G. Favor, San Francisco, CA (US); Michael N. Michael, Folsom, CA (US); and Vihar Soneji, Newark, CA (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on Jun. 8, 2022, as Appl. No. 17/835,352.
Prior Publication US 2023/0401063 A1, Dec. 14, 2023
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3802 (2013.01) [G06F 9/3806 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An instruction fetch pipeline, comprising:
a first sub-pipeline that includes a translation lookaside buffer (TLB) configured to receive a fetch virtual address;
a second sub-pipeline that includes a tag random access memory (RAM) of a physically-indexed physically-tagged set associative instruction cache configured to receive a predicted set index, wherein the predicted set index specifies a set of the instruction cache that includes an entry from which a block of instructions specified by the fetch virtual address was previously fetched; and
a third sub-pipeline that includes a data RAM of the instruction cache configured to receive the predicted set index and a predicted way number that specifies a way of the entry from which the block of instructions was previously fetched;
wherein the first, second and third sub-pipelines are configured to respectively initiate in parallel:
access of the TLB using the fetch virtual address to obtain a translation thereof into a fetch physical address that includes a tag;
access of the tag RAM using the predicted set index to read a set of tags; and
access of the data RAM using the predicted set index and the predicted way number to fetch the block of instructions.