US 12,014,175 B2
Data processing system and operation method of data processing system
Shunpei Yamazaki, Setagaya (JP); Hajime Kimura, Atsugi (JP); and Tatsuya Onuki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jun. 20, 2022, as Appl. No. 17/844,213.
Application 17/844,213 is a continuation of application No. 17/074,872, filed on Oct. 20, 2020, granted, now 11,379,231.
Claims priority of application No. 2019-194589 (JP), filed on Oct. 25, 2019.
Prior Publication US 2022/0318011 A1, Oct. 6, 2022
Int. Cl. G06F 9/30 (2018.01); G11C 11/402 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 9/3004 (2013.01); G11C 11/4023 (2013.01); G11C 11/4085 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells including a first memory region and a second memory region,
wherein, when the memory device is activated, the second memory region includes a first space in which binary data are stored, a second space in which multilevel data are stored, and a free space,
wherein the first memory region is a volatile memory,
wherein the first memory region is a first main memory device,
wherein the free space is configured to be used as a second main memory device,
wherein the first memory region and the free space are configured to be used when an arithmetic processing is performed, and
wherein the second main memory device is a nonvolatile memory.