US 12,014,150 B2
Multiple mode arithmetic circuit
Daniel Pugh, Los Gatos, CA (US); Raymond Nijssen, San Jose, CA (US); Michael Philip Fitton, Menlo Park, CA (US); and Marcel Van der Goot, Pasadena, CA (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on Mar. 23, 2023, as Appl. No. 18/125,190.
Application 18/125,190 is a continuation of application No. 17/569,801, filed on Jan. 6, 2022, granted, now 11,650,792.
Application 17/569,801 is a continuation of application No. 16/535,878, filed on Aug. 8, 2019, granted, now 11,256,476.
Prior Publication US 2023/0244446 A1, Aug. 3, 2023
Int. Cl. G06F 7/487 (2006.01); G06F 7/53 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/4876 (2013.01) [G06F 7/5324 (2013.01); G06F 7/5443 (2013.01); G06F 2207/3824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field programmable gate array (FPGA) comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode and a second mode;
a plurality of integer arithmetic logic blocks; and
a plurality of output connections;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform a real multiplication on first integer operands of a first size;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform a complex multiplication on second integer operands of a second size that is smaller than the first size; and
in the first mode and the second mode, the plurality of output connections provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.