	US 12,014,129 B2
	Circuit design visibility in integrated circuit devices
Yi Peng, Newark, CA (US); and Brandon Lewis Gordon, Campell, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,208.
Prior Publication US 2021/0012051 A1, Jan. 14, 2021
Int. Cl. G06F 30/343 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01)

CPC G06F 30/343 (2020.01) [G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01)]

9 Claims

1. A method comprising:

retrieving, at a host device, a circuit design configured to implement a circuit on an integrated circuit device, wherein the circuit comprises a set of registers and a set of inputs associated with at least one register of the set of registers;

receiving, at the host device, a selection of a portion of the circuit based on the circuit design;

selecting, at the host device, a first subset of the set of registers and a subset of the set of inputs based on the selection; and

generating, at the host device, instrumentation logic based on the selected first subset of the set of registers, wherein the instrumentation logic is configured to collect signal data from the selected first subset of the set of registers during implementation of the circuit on the integrated circuit device.