US 12,014,127 B2
Transforming a logical netlist into a hierarchical parasitic netlist
Jeffrey C. Herbert, Naples, FL (US); Matthew Christopher Lanahan, Fairfield, VT (US); and John Edward Barth, Williston, VT (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 9, 2022, as Appl. No. 17/668,180.
Prior Publication US 2023/0252208 A1, Aug. 10, 2023
Int. Cl. G06F 30/323 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/323 (2020.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a logical netlist file for a memory device and placement information for the memory device, the logical netlist file includes memory instances of the memory device, wherein each memory instance includes leaf cells;
determining a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance of the memory instances based on the placement information;
generating a first net segment between the first leaf cell and the second leaf cell based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell; and
generating, by a processor, a parasitic netlist based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.