US 12,014,088 B2
Memory sub-system storage mode control
Thomas Pratt, Austin, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/887,900.
Application 17/887,900 is a continuation of application No. 16/990,913, filed on Aug. 11, 2020, granted, now 11,416,177.
Prior Publication US 2022/0391145 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G11C 11/56 (2013.01); G11C 13/0002 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device comprising memory cells; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
asserting a flag indicating that data written to the memory cells in an SLC mode is to remain stored in the SLC mode; and
in response to determination of an event, de-asserting the flag, thereby indicating that the data is foldable into memory cells in a non-SLC mode.