US 12,014,084 B2
Data memory access collision manager, device and method
Fabio Enrico Carlo Disegni, Spino d'Adda (IT); Federico Goller, Turin (IT); Dario Falanga, Vimercate (IT); Michele Febbrarino, Bagheria (IT); and Massimo Montanaro, Cava Manara (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Feb. 10, 2022, as Appl. No. 17/669,085.
Prior Publication US 2023/0251795 A1, Aug. 10, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A device, comprising:
a plurality of sets of registers, which, in operation, store addresses and data associated with data read requests received from respective processing cores of a plurality of processing cores, the data read requests being directed to a data partition of a non-volatile memory; and
control circuitry coupled to the plurality of sets of registers, wherein the control circuitry, in a read-while-write collision management mode of operation, responds to a data read request received from one processing core of the plurality of processing cores and directed to the data partition by:
storing an address associated with the data read request in an address register of one of the plurality of sets of registers associated with the one processing core;
requesting suspension of write operations directed to the data partition;
in response to an acknowledgement of suspension of the write operations, requesting execution of a read operation associated with the read request while the write operations are suspended;
storing data responsive to the read operation in one or more data registers of the one of the plurality of sets of registers; and
providing the data stored in the one or more data registers of the one of the plurality of sets of registers to the one processing core.