US 12,014,080 B2
Memory system using host memory buffer and operation method thereof
Bumhee Lee, Suwon-si (KR); Wooram Kim, Suwon-si (KR); Hyunseok Kim, Suwon-si (KR); Kihyun Park, Suwon-si (KR); Sooyun Lee, Suwon-si (KR); Hyeongyu Cho, Suwon-si (KR); and Shin-Ho Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 2, 2022, as Appl. No. 17/979,554.
Claims priority of application No. 10-2021-0154276 (KR), filed on Nov. 10, 2021; and application No. 10-2022-0055613 (KR), filed on May 4, 2022.
Prior Publication US 2023/0142174 A1, May 11, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 1/3203 (2019.01); G06F 12/02 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 1/3203 (2013.01); G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0679 (2013.01); G06F 12/0223 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An operation method of a memory system which includes a host and a storage device, the method comprising:
allocating a portion of a host memory included in the host as a host memory buffer for the storage device;
setting a set feature command to enable the host memory buffer;
setting a retention command comprising information about a response speed of the host memory buffer;
selecting an operation mode of the host memory buffer, based on the retention command; and
selecting a power state, among a plurality of power states supported by a controller of the storage device, based on a performance objective of the operation mode of the host memory buffer.