US 12,014,071 B2
Separation of parity columns in bit-flip decoding of low-density parity-check codes with pipelining and column parallelism
Eyal En Gad, Highland, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); and Yoav Weinberg, Thornhill (CA)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,080.
Prior Publication US 2023/0195358 A1, Jun. 22, 2023
Int. Cl. H03M 13/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A decoder, comprising:
a plurality of circuits configured to perform parallel computation in bit-flipping, wherein decoding of a codeword is according to a parity matrix, and the parallel computation is by the plurality of circuits according to a first plurality of columns of the parity matrix respectively; and
a logic circuit configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits include no more than one parity column of the parity matrix.