US 12,014,066 B2
Selective use of high-performance memory in a software defined system
Kenny Van Alstyne, Mechanicsville, VA (US); and Phillip Edward Straw, Newark, CA (US)
Assigned to SOFTIRON LIMITED, London (GB)
Filed by SOFTIRON LIMITED, Chilworth (GB)
Filed on Sep. 2, 2022, as Appl. No. 17/902,598.
Claims priority of provisional application 63/241,828, filed on Sep. 8, 2021.
Prior Publication US 2023/0273739 A1, Aug. 31, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/065 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/067 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an interface to a plurality of non-volatile random-access memory (NV-RAM) configured to receive results of a hardware accelerator; and
a memory management circuit configured to:
access the plurality of non-volatile random access memory;
access a software-defined-system (SDS), the SDS to manage replication of data across a cluster of memory devices;
generate a block device from the plurality of NV-RAM;
determine that the block device is to be used to receive results of the hardware accelerator, the hardware accelerator to create the results from execution of a workload, the results from execution of the workload to be replicated in the SDS in at least one other storage location;
determine that the results of the hardware accelerator as stored in the block device are to be replicated in the SDS;
based on a determination that the results of the hardware accelerator as stored in the block device are to be replicated in the SDS, configure the block device for use with the SDS, the block device configured to be included by the SDS in the cluster of memory devices and be controlled by the memory management circuit after inclusion in the cluster of memory devices; and
configure the block device to be replicated by an SDS manager application of the SDS system while retaining selective control by the memory management circuit for access to and replication of the block device, including to:
cause one or more workloads to be loaded into the hardware accelerator for execution and the results from the one or more workloads to be stored in the block device as part of the SDS;
during execution of the one or more workloads and storing of the results into the block device, turn off replication of the block device in the SDS while maintaining the block device as part of the SDS; and
upon completion of execution of the one or more workloads and storing of the results into the block device, turn on replication of the block device in the SDS.