US 12,014,060 B2
Memory calibration and margin check
Robert E. Jeter, Santa Clara, CA (US); Jingkui Zheng, Santa Clara, CA (US); Ritesh J. Shah, Sunnyvale, CA (US); Veera Chockalingam, Santa Clara, CA (US); and Naveen Kumar Korada, Round Rock, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 1, 2022, as Appl. No. 17/929,212.
Prior Publication US 2024/0078029 A1, Mar. 7, 2024
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 29/50 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 29/50 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method, comprising:
performing, by a memory controller during an initialization process, horizontal memory calibrations for ones of a plurality of performance states;
determining, by the memory controller, a set of differences between calibration results for pairs of the plurality of performance states;
storing, by the memory controller, information indicative of the set of differences;
subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states:
setting initial memory parameters for the second one of the plurality of performance states that are based on the set of differences; and
beginning operation in the second one of the plurality of performance states using the initial memory parameters without performing an initial horizontal memory calibration.